Digital Logic · topic
SR, D, JK and T latches and flip-flops with characteristic and excitation tables, level versus edge triggering, setup, hold and maximum clock frequency, shift registers, ripple, synchronous, mod-N, ring and Johnson counters, counter design and lockout, Moore and Mealy machines, state minimisation and sequence detectors.
SR latches built from NOR (active-high) and NAND (active-low) gates and their forbidden inputs, gated and D latches, level versus edge triggering with a simulated timing diagram, SR, JK, D and T characteristic tables and equations, the excitation table, flip-flop conversions, race-around and master-slave, asynchronous preset and clear, setup, hold and clock-to-Q, and the minimum clock period with and without skew.
A partial preview of the top of the sheet. The full sheet is in the Digital Logic cheat sheet pack.
Shift registers and their clock counts, ripple (asynchronous) counters with count direction by edge and output, settling delay and transient states, synchronous binary counters and their maximum frequency, mod-N counters with asynchronous clear, ring and Johnson counters with unused and lockout states, frequency division, and a synchronous counter designed with D and JK flip-flops including its unused-state check. All sequences simulated.
A partial preview of the top of the sheet. The full sheet is in the Digital Logic cheat sheet pack.
Moore versus Mealy machines and their output timing, the overlapping 101 detector in both models with state diagrams and tables, overlapping versus non-overlapping detection, minimum state counts for k-bit patterns, the synchronous FSM design routine, state minimisation by partition refinement on a worked table, flip-flop counts for binary and one-hot assignment. State counts, tables and output strings generated by script.
A partial preview of the top of the sheet. The full sheet is in the Digital Logic cheat sheet pack.
