Digital Logic · topic
Half and full adders and subtractors, ripple-carry and carry-lookahead delay with generate and propagate, adder-subtractor, comparators, multiplexers and implementing functions with them, mux and decoder trees, decoders, encoders and priority encoders, static hazards, and ROM sizing.
Half and full adders and subtractors with truth tables and equations, a full adder from two half adders, the ripple-carry adder and its delay in a per-stage model and a gate model, carry lookahead with generate and propagate, the 4-bit lookahead structure and its delay and gate-count growth, block lookahead for 16 bits, the adder-subtractor, and 1-bit and 4-bit magnitude comparators. Truth tables, equations and delays checked by script over all inputs.
A partial preview of the top of the sheet. The full sheet is in the Digital Logic cheat sheet pack.
Multiplexer equations and the implementation-table method for realising an (n+1)-variable function on a 2^n:1 mux, the 2:1 mux as a universal element, mux trees and decoder trees with block counts, decoders as minterm generators with active-high and active-low outputs, encoders and the 4:2 priority encoder, static hazards and the consensus cure, and ROM sizing. Every realisation simulated over all inputs.
A partial preview of the top of the sheet. The full sheet is in the Digital Logic cheat sheet pack.
