Computer Organization & Architecture · topic
Pipeline clock from stage and latch delays, total time, speedup, efficiency, throughput and CPI; data hazards with space-time diagrams, stalls and forwarding; control hazards with branch penalties, prediction and delay slots; structural hazards and combined CPI.
Instruction pipelining: clock period from the slowest stage plus latch delay, total time for n instructions, speedup and its limit, efficiency and throughput, unequal stages and stage splitting, latency, CPI with stall cycles and speedup against a multi-cycle machine, with two solved past GATE questions and original examples, all computed by script.
A partial preview of the top of the sheet. The full sheet is in the Computer Organization & Architecture cheat sheet pack.
Data hazards in the 5-stage pipeline: RAW, WAR, WAW and RAR dependences, a space-time diagram of a load and two dependent instructions with and without forwarding, the stall table by producer type and distance, the stall formula with and without a split-cycle register file, how the forwarding unit and the load-use detector work, removing a stall by scheduling, and a solved past GATE question on dependences.
A partial preview of the top of the sheet. The full sheet is in the Computer Organization & Architecture cheat sheet pack.
Control hazards: branch penalty from the stage where the branch resolves, CPI under stall-always, predict-not-taken and dynamic prediction worked with one set of numbers, delayed branches, 1-bit and 2-bit predictors simulated on a loop, structural hazards from a single memory port or a non-pipelined unit, and the combined CPI and speedup when data, control and structural stalls add up.
A partial preview of the top of the sheet. The full sheet is in the Computer Organization & Architecture cheat sheet pack.
