Computer Organization & Architecture · topic
I/O interfaces, memory-mapped and isolated I/O, programmed I/O, the interrupt sequence, vectored and daisy-chain priority, masking and nesting, CPU overhead of polling and interrupts, and DMA: controller, bus handshake, burst, cycle-stealing and transparent modes with CPU-time fractions.
The I/O interface and its data, status and control registers, memory-mapped versus isolated I/O, programmed I/O with polling, the interrupt sequence with a solved past GATE question, finding the source by polling, daisy chain, priority encoder or vector, masking, priority and nesting, interrupts versus exceptions, and the CPU time spent on polling, interrupts and DMA worked with one set of numbers.
A partial preview of the top of the sheet. The full sheet is in the Computer Organization & Architecture cheat sheet pack.
Direct memory access: the DMA controller and its registers, the bus request and grant handshake, the steps of a transfer, burst, cycle-stealing and transparent modes compared, the CPU-blocked fraction and the cycle-stealing rate formulas, a solved past GATE question on transfer rate, block-time and CPU-loss examples, when the bus can be granted, DMA against interrupt overhead and the cache-coherence caveat.
A partial preview of the top of the sheet. The full sheet is in the Computer Organization & Architecture cheat sheet pack.
