Computer Organization & Architecture · topic
Instruction formats and field widths, counting instructions with expanding opcodes, zero- to three-address code, instruction types, RISC versus CISC, condition flags, byte ordering and alignment, and every addressing mode with its effective-address rule, memory-reference count and typical use.
Fixed-length instruction formats: opcode, mode, register, address and immediate fields, each sized with a ceiling log. Zero-, one-, two- and three-address code for one expression with instruction counts, data references and code size. Expanding opcodes level by level with a Kraft-style feasibility check, and three solved past GATE questions on field budgets and expanding opcodes.
A partial preview of the top of the sheet. The full sheet is in the Computer Organization & Architecture cheat sheet pack.
The instruction set architecture (ISA): instruction types, ISA classes by where ALU operands live, RISC versus CISC, the CPU-time equation with a worked comparison, condition flags with the signed and unsigned compare rules, big- and little-endian byte order with a byte table, alignment, CALL and RET on a downward stack, and what belongs to the ISA versus the implementation.
A partial preview of the top of the sheet. The full sheet is in the Computer Organization & Architecture cheat sheet pack.
Every addressing mode with its effective-address (EA) rule, the memory reads needed to reach the operand and its typical use: immediate, register, direct, indirect, register indirect, indexed, base plus displacement, PC-relative, auto-increment, auto-decrement and implied. One instruction worked in every mode, PC-relative offsets and ranges, relocation, memory references per instruction and the usual traps.
A partial preview of the top of the sheet. The full sheet is in the Computer Organization & Architecture cheat sheet pack.
