Computer Organization & Architecture · topic
The last three sheets: traps that cost marks with the rule that fixes each, question patterns with the routine to run, and a one-page master sheet of formulas, tables and numbers to recognise.
The common wrong turns in Computer Organization questions, grouped from instruction formats to pipeline hazards: each row gives the wrong belief, the correct rule and a checked number or pointer to the sheet that explains it. Covers field widths, expanding opcodes, addressing, overflow, Booth, microinstruction widths, chip arrays, access-time models, cache splits and write policies, interrupts, DMA, pipeline time, forwarding and branch penalties.
A partial preview of the top of the sheet. The full sheet is in the Computer Organization & Architecture cheat sheet pack.
Recognition cues for the usual Computer Organization question types, each with the first step and method to run and the assumption or slip to check, from instruction formats and addressing through ALU delays, control memory, chip arrays, access time, cache splits and traces, write policies, interrupts and DMA to pipeline time, stalls and branches. Ends with a general routine for numericals and answer-size sanity checks.
A partial preview of the top of the sheet. The full sheet is in the Computer Organization & Architecture cheat sheet pack.
One-page summary of the pack: field widths and expanding opcodes, addressing-mode reads, adder delays, overflow and Booth, control steps and control-memory size, chip arrays, access-time formulas, the cache split with its worked table, write policies, interrupt order and DMA formulas, pipeline time and CPI, the stall table and branch penalties, with the numbers worth recognising and the last-minute checks.
A partial preview of the top of the sheet. The full sheet is in the Computer Organization & Architecture cheat sheet pack.
