Computer Organization & Architecture · topic
Building a memory from smaller chips: chip counts, decoders, address maps, partial decoding, DRAM address multiplexing and interleaving. Then locality, hit ratio and average access time for hierarchical and simultaneous access, multilevel formulas and memory stall cycles.
Building a memory from smaller chips: chip pins and capacity, chip count for width and depth expansion, the row decoder on the high address bits, address ranges per row, which chip holds a given address, a byte-addressable 2 MB example, full versus partial decoding and aliasing, DRAM row and column address multiplexing with refresh overhead, SRAM versus DRAM, and low- and high-order interleaving.
A partial preview of the top of the sheet. The full sheet is in the Computer Organization & Architecture cheat sheet pack.
Locality and the levels of the hierarchy, hit ratio, average access time for hierarchical (look-through) and simultaneous (look-aside) access, solving for a target hit ratio, block refill time, three-level formulas in both models, local versus global miss rates, memory stall cycles in CPI with two solved past GATE questions, and average cost per unit of storage.
A partial preview of the top of the sheet. The full sheet is in the Computer Organization & Architecture cheat sheet pack.
